This Project deals with the porting of Micro C/OS-II kernel in ARM powered microcontroller for the implementation of multitasking and time scheduling. Here a real time kernel is the software that manages the time of a micro controller to ensure that all time critical events are processed as efficiently as possible.
We have applied advanced real-time techniques software, that are intensively used in critical areas like space research and defense applications, to realize an industrial real time parameter Monitoring System. The heart of the system is a real-time kernel that uses preemptive scheduling to achieve multitasking on hardware platform. The Arm processor gets all relevant information from one source i.e. the remote terminal section. The temperature analysis data is plotted in convenient diagram in graphical LCD. The trend of all these parameters is available with a granularity of one minute.
We have applied advanced real-time techniques software, that are intensively used in critical areas like space research and defense applications, to realize an industrial real time parameter Monitoring System. The heart of the system is a real-time kernel that uses preemptive scheduling to achieve multitasking on hardware platform. The Arm processor gets all relevant information from one source i.e. the remote terminal section. The temperature analysis data is plotted in convenient diagram in graphical LCD. The trend of all these parameters is available with a granularity of one minute.
Fig 1.1: Multitasking
In this project we are going to perform multitasking simultaneously. In Micro C/OS-II maximum number of task is 64, but here we going to perform up to 6 tasks the tasks like LED scrolling, alarm, temperatures sensor, graphical LCD, serial communication, relay are perform simultaneously.
1.1. Existing System
General-computing non-real-time operating systems are often quite non-deterministic. Their services can inject random delays into application software and thus cause slow responsiveness of an application at unexpected times. Other problems in this kind of system are single program approach (one task), power consumption problem.
General-computing non-real-time operating systems are often quite non-deterministic. Their services can inject random delays into application software and thus cause slow responsiveness of an application at unexpected times. Other problems in this kind of system are single program approach (one task), power consumption problem.
1.2. Proposed System
In this paper, the proposed method is implemented on a coarse grain reconfigurable architecture with 8 and 32 processing elements. A large amount of random scenario have been simulated and the statistical results presented here clearly show real advantages of the proposed method, but also some limitations drawing the line of future works. The design of embedded systems has become more complex than ever, and the design qualities depend more on the cooperation of multidisciplinary design teams: hardware engineers and software engineers in general.
However, due to the lack of uniform programming model and system components for these different teams, the migrations costs of a function model from software to hardware are high. But these actions are necessary in the hardware-software partitioning of embedded systems, especially in the prototype designs. To cope with this problem, we adopt a uniform multi-task model and implement Micro C/OS-II RTOS(Real- Time Operating System).
CHAPTER 2
EMBEDDED SYSTEM
An embedded system is a special-purpose computer system designed performs one or a few dedicated functions, often with real-time computing constraint [2]. In general, embedded system means the processors is embedded into that application. The majority of computer system in use today is embedded in other machinery, such as telephones, clocks, applications and vehicles.
An embedded system may have minimal requirement for memory and program length. Input and output devices may be discrete switches, relays or solenoids. An embedded controller may lack human-readable interface devices. For example, embedded systems usually don’t have keyboards, screen, disks, printers or other recognizable I/O devices of a personal computer.
Microcontrollers may control electric motors, relays, voltages and many read switches, variable resistors and other electronic devices. An embedded product uses either a microcontroller or microprocessors to do one task at a time .in an embedded system, there is only one application software that is typically burned into ROM. Example, printer, keyboard, video game player, etc…
An embedded system is a special-purpose computer system designed performs one or a few dedicated functions, often with real-time computing constraint [2]. In general, embedded system means the processors is embedded into that application. The majority of computer system in use today is embedded in other machinery, such as telephones, clocks, applications and vehicles.
An embedded system may have minimal requirement for memory and program length. Input and output devices may be discrete switches, relays or solenoids. An embedded controller may lack human-readable interface devices. For example, embedded systems usually don’t have keyboards, screen, disks, printers or other recognizable I/O devices of a personal computer.
Microcontrollers may control electric motors, relays, voltages and many read switches, variable resistors and other electronic devices. An embedded product uses either a microcontroller or microprocessors to do one task at a time .in an embedded system, there is only one application software that is typically burned into ROM. Example, printer, keyboard, video game player, etc…
2.1. Characteristics
1. Embedded system is designed to do some specific task, rather than a general purpose computer for multiple tasks. Some also have real-time performance constraints that must be met, for reason such as safety and usability; others may have low or no performance requirement, allowing the system hardware to be simplified to reduce cost.
2. Embedded systems are not always separate devices [2]. Most often they are physically built-in to the devices they control.
3. The software written for the computer systems is often called firmware, and is stored in read-only memory or flash memory chips rather than disk drives. It often runs with limited computer hardware resources small or no keyboard, screen and little memory.
2.2. Real-Time Embedded Systems
In the simplest form, real-time systems can be defined as those systems that respond to external events in a timely fashion, the response time is guaranteed [4]. We revisit this definition after presenting some examples of real-time systems.
In the simplest form, real-time systems can be defined as those systems that respond to external events in a timely fashion, the response time is guaranteed [4]. We revisit this definition after presenting some examples of real-time systems.
Fig 2.1: A simple view of real-time systems
External events can have synchronous or asynchronous characteristics. Responding to external events includes recognizing when an event occurs, performing the required processing as a result of the event, and outputting the necessary results within a given time constraint. Timing constraints include finish time, or both start time and finish time.A good way to understand the relationship between real-time systems and embedded systems is to view them as two intersecting circles, as shown in. It can be seen tha0t not all embedded systems exhibit real-time behaviors nor are all real-time systems embedded. However, the two systems are not mutually exclusive, and the area in which they overlap creates the combination of systems known as real-time embedded systems.
Fig 2.2: Real-time embedded systems Knowing this fact and because we have covered the various aspects of embedded systems in the previous sections, we can now focus our attention on real-time systems.
2.3. Peripherals
Embedded system talk with the outside world via peripherals, such as
· Serial communication interfaces (SCI): RS-232, RS-422, RS-485 etc.
· Synchronous serial communication interfaces: 12C, JTAG, SPI, SSC, AND ESSI.
· Universal serial bus(USB)
· Networks: Ethernet, Controller Area Network, LAN Works etc.
· Timers: PLL(s) capture/compare and Time Processing Units.
· Discrete I/O: General Purpose Input/output (GPIO).
. Analog to Digital/Digital to Analog (ADC/DAC).
CHAPTER 3
REAL TIME OPERATING SYSTEM
3.1. Real-Time System
Definition:
A real-time system (defined by IEEE) is a system whose correctness includes its response time as well as its functional correctness.
In other words, in a real-time system, it not only matters that the answers are correct, but it matters when the answers are produced [4].
Definition:
A real-time system (defined by IEEE) is a system whose correctness includes its response time as well as its functional correctness.
In other words, in a real-time system, it not only matters that the answers are correct, but it matters when the answers are produced [4].
A Late Answer is a Wrong Answer!
3.1.1. Real-Time Systems – Categories
1. Hard Real-Time Systems
2. Soft Real-Time Systems
Hard Real-Time Systems
Hard real-time means that the system (i.e., the entire system including OS, middleware, application, HW, communications, etc.) must be designed to GUARANTEE that response requirements are met. Hard Real-Time doesn’t mean fast execution. Examples:Electronic Engines, Automotive and Flight Control Systems, Medical Systems, Industrial Control Systems, Robotics.
Hard real-time means that the system (i.e., the entire system including OS, middleware, application, HW, communications, etc.) must be designed to GUARANTEE that response requirements are met. Hard Real-Time doesn’t mean fast execution. Examples:Electronic Engines, Automotive and Flight Control Systems, Medical Systems, Industrial Control Systems, Robotics.
Soft-Real Time Systems
Soft real-time is exactly the same as hard real-time in its infrastructure requirements, but it is not necessary for system success that EVERY time constraint be met. Example:Telecommunication Systems, Internet Video, ATM
Soft real-time is exactly the same as hard real-time in its infrastructure requirements, but it is not necessary for system success that EVERY time constraint be met. Example:Telecommunication Systems, Internet Video, ATM
Fig 3.1: The Real-Time Spectrum
3.1.2. Real-Time Design Approaches
• There are two primary techniques used in real-time designs
- Super- loops
One program running
-Multitasking
Many programs running, taking turns.
Super-Loops
Super loops also called Foreground/Background Systems.There is a background loop that is always running anytime an ISR isn’t executing.The CPU is always busy. Small system of low complexity is generally designed as shown figure [1]. An application consists of an infinite loop that calls modules to perform the desired operation (background). Interrupt services routine handle asynchronous events (foreground). Foreground is also called interrupt level; background is called task level. Critical operation must be performed by the ISR is ensure that they are dealt with in a timely fashion. Because of this ISR have a tendency to take longer than they should. Also, information for a background module made available by an ISR is not processed until the background routine gets its turn to execute. This is called the task level response. The worst-case task level response time depends on how long the background loop takes to executes. Because of the execution time of typical code is not constant; the time for successive passes through a portion of the loop is nondeterministic.
Super loops also called Foreground/Background Systems.There is a background loop that is always running anytime an ISR isn’t executing.The CPU is always busy. Small system of low complexity is generally designed as shown figure [1]. An application consists of an infinite loop that calls modules to perform the desired operation (background). Interrupt services routine handle asynchronous events (foreground). Foreground is also called interrupt level; background is called task level. Critical operation must be performed by the ISR is ensure that they are dealt with in a timely fashion. Because of this ISR have a tendency to take longer than they should. Also, information for a background module made available by an ISR is not processed until the background routine gets its turn to execute. This is called the task level response. The worst-case task level response time depends on how long the background loop takes to executes. Because of the execution time of typical code is not constant; the time for successive passes through a portion of the loop is nondeterministic.
Foreground/Background System
Disadvantage
- Background response time is the background execution time
– Non-deterministic
§ Affected by if, for, while ...
– May not be responsive enough
– Changes as you change your code
- All ‘tasks’/functions () have the same priority!
– Code executes in sequence
– If an important event occurs it’s handled at the same priority as everything else!
– You may need to execute the same code often to avoid missing an event.
3.2. Introduction to RTOS
A real-time operating system (RTOS) is key to many embedded systems today and, provides a software platform upon which to build applications [1]. Not all embedded systems, however, are designed with an RTOS. Some embedded systems with relatively simple hardware or a small amount of software application code might not require an RTOS. Many embedded systems, however, with moderate-to-large software applications require some form of scheduling, and these systems require an RTOS. This chapter sets the stage for all subsequent chapters in this section. It describes the key concepts upon which most real-time operating systems are based.
A real-time operating system (RTOS) is key to many embedded systems today and, provides a software platform upon which to build applications [1]. Not all embedded systems, however, are designed with an RTOS. Some embedded systems with relatively simple hardware or a small amount of software application code might not require an RTOS. Many embedded systems, however, with moderate-to-large software applications require some form of scheduling, and these systems require an RTOS. This chapter sets the stage for all subsequent chapters in this section. It describes the key concepts upon which most real-time operating systems are based.
3.2.1. Defining an RTOS
A real-time operating system (RTOS) is a program that schedules execution in a timely manner, manages system resources, and provides a consistent foundation for developing application code. For example, in some applications, an RTOS comprises only a kernel, which is the core supervisory software that provides minimal logic, scheduling, and resource-management algorithms.
Although many RTOSes can scale up or down to meet application requirements, this book focuses on the common element at the heart of all RTOSes-the kernel [3]. Most RTOS kernels contain the following components:
A real-time operating system (RTOS) is a program that schedules execution in a timely manner, manages system resources, and provides a consistent foundation for developing application code. For example, in some applications, an RTOS comprises only a kernel, which is the core supervisory software that provides minimal logic, scheduling, and resource-management algorithms.
Although many RTOSes can scale up or down to meet application requirements, this book focuses on the common element at the heart of all RTOSes-the kernel [3]. Most RTOS kernels contain the following components:
Scheduler-is contained within each kernel and follows a set of algorithms that determines which task executes when.
Objects-are special kernel constructs that help developers create applications for real-time embedded systems. Common kernel objects include tasks, semaphores, and message queues.
Services-are operations that the kernel performs on an object or, generally operations such as timing, interrupt handling, and resource management.
Common components in an RTOS kernel that including objects, the scheduler, and some services. This diagram is highly simplified; remember that not all RTOS kernels conform to this exact set of objects, scheduling algorithms, and services.
Common components in an RTOS kernel that including objects, the scheduler, and some services. This diagram is highly simplified; remember that not all RTOS kernels conform to this exact set of objects, scheduling algorithms, and services.
3.3. Commercial RTOSs
C/OS-II, VxWorks, pSOS System, Nucleus, Windows CE
3.4. RTOS Advantages
• Software that manages the time of a microprocessor or microcontroller
– Ensures that the most important code runs first
• Allows Multitasking
– Do more than one thing at the same time
– Application is broken down into multiple tasks, each handling one aspect of your application
– It’s like having multiple CPUs
• Provides valuable services to your application
– Time delays, Resource sharing.
– Inter-task communication and synchronization.
CHAPTER 4
C/OS-II
4.1. Why we choose Micrium µC/OS-II
• Written in ANSI C
– Source code provided
– Consistent coding style
• Pre-emptive
• Deterministic
• Royalty-free
– Licensed on a per-end-product basis
• Extensive Documentation and Support
• Meets requirements of Safety-Critical Systems
• Large user base
– Used in hundreds of products all over the world
4.2. C/OS-II
Written by Jean J. Labrosse in ANSI C .A portable, ROMable, scalable, preemptive, real-time, multitasking kernel .Used in hundreds of products since its introduction in 1992[1] .Certified by the FAA for use in commercial aircraft .Available in ARM Firmware Suite (AFS) .Over 90 ports for free download
Written by Jean J. Labrosse in ANSI C .A portable, ROMable, scalable, preemptive, real-time, multitasking kernel .Used in hundreds of products since its introduction in 1992[1] .Certified by the FAA for use in commercial aircraft .Available in ARM Firmware Suite (AFS) .Over 90 ports for free download
4.2.1. Overview to µC/OS-II
MicroC/OS-II (commonly termed µC/OS-II or uC/OS-II), is a low-cost priority-based pre-emptive real time multitasking operating system kernel for microprocessors, written mainly in the C programming language. It is mainly intended for use in embedded systems. UC/OS-II is currently maintained by Micrium Inc. and can be licensed on as per product or product line basis. Use of the operating system is free for educational non-commercial use. Additionally, Micrium provides other middleware software products such as uC/OS-View, uC/CAN, uC/TCP-IP, uC/FS, uC/GUI, uC/MOD-BUS, uC/LCD, uC/USB (Mass Storage Device and Bulk) and a large assortment of uC/TCP-IP applications such as client software for DHCP, POP3, SNTP, FTP, TFTP, DNS, SMTP, and TTCP [1]. Server software includes HTTP, FTP, and TFTP. PPP is also available.
To describes the design and implementation of µC/OS-II (pronounced "Micro C O S 2"), which stands for Microcontroller Operating System Version 2. µC/OS-II is based on µC/OS, The Real-Time Kernel that was first published in 1992. Thousands of people around the world are using µC/OS in all kinds of applications, such as cameras, medical instruments, musical instruments, engine controls, network adapters, highway telephone call boxes, ATM machines, industrial robots, and more. Numerous colleges and universities also have used µC/OS to teach students about real-time systems.
µC/OS-II is upward compatible with µC/OS V1.11 but provides many improvements, such as the addition of a fixed-sized memory manager; user-definable callouts on task creation, task deletion, task switch, and system tick; TCB extensions support; stack checking; and much more. I also added comments to just about every function, and I made µC/OS-II much easier to port to different processors. The source code in µC/OS was placed in two files. Because µC/OS-II contains many new features and functions, I decided to split µC/OS-II into a few source files to make the code easier to maintain.
MicroC/OS-II (commonly termed µC/OS-II or uC/OS-II), is a low-cost priority-based pre-emptive real time multitasking operating system kernel for microprocessors, written mainly in the C programming language. It is mainly intended for use in embedded systems. UC/OS-II is currently maintained by Micrium Inc. and can be licensed on as per product or product line basis. Use of the operating system is free for educational non-commercial use. Additionally, Micrium provides other middleware software products such as uC/OS-View, uC/CAN, uC/TCP-IP, uC/FS, uC/GUI, uC/MOD-BUS, uC/LCD, uC/USB (Mass Storage Device and Bulk) and a large assortment of uC/TCP-IP applications such as client software for DHCP, POP3, SNTP, FTP, TFTP, DNS, SMTP, and TTCP [1]. Server software includes HTTP, FTP, and TFTP. PPP is also available.
To describes the design and implementation of µC/OS-II (pronounced "Micro C O S 2"), which stands for Microcontroller Operating System Version 2. µC/OS-II is based on µC/OS, The Real-Time Kernel that was first published in 1992. Thousands of people around the world are using µC/OS in all kinds of applications, such as cameras, medical instruments, musical instruments, engine controls, network adapters, highway telephone call boxes, ATM machines, industrial robots, and more. Numerous colleges and universities also have used µC/OS to teach students about real-time systems.
µC/OS-II is upward compatible with µC/OS V1.11 but provides many improvements, such as the addition of a fixed-sized memory manager; user-definable callouts on task creation, task deletion, task switch, and system tick; TCB extensions support; stack checking; and much more. I also added comments to just about every function, and I made µC/OS-II much easier to port to different processors. The source code in µC/OS was placed in two files. Because µC/OS-II contains many new features and functions, I decided to split µC/OS-II into a few source files to make the code easier to maintain.
4.2.2. MicroC/OS using ARM
µC/OS-II, The Real-Time Kernel is a highly portable, ROMable, very scalable, preemptive real-time, multitasking kernel (RTOS) for microprocessors and microcontrollers. µC/OS-II can manage up to 250 application tasks. A validation suite has been developed for µC/OS-II and provides all the documentation necessary to prove that µC/OS-II is suitable for Safety Critical Systems common to Aviation and Medical products. Although this feature may not be applicable to your needs, it does prove that µC/OS-II is a very robust RTOS.
µC/OS-II runs on a large number of processor architectures and ports. The vast number of ports should convince you that µC/OS-II is truly very portable and thus will most likely be ported to new processors as they become available.
µC/OS-II can be scaled to only contain the features you need for your application and thus provide a small footprint. Depending on the processor, on an ARM (Thumb mode) µC/OS-II can be reduced to as little as 6K bytes of code space and 500 bytes of data space (excluding stacks).
µC/OS-II, The Real-Time Kernel is a highly portable, ROMable, very scalable, preemptive real-time, multitasking kernel (RTOS) for microprocessors and microcontrollers. µC/OS-II can manage up to 250 application tasks. A validation suite has been developed for µC/OS-II and provides all the documentation necessary to prove that µC/OS-II is suitable for Safety Critical Systems common to Aviation and Medical products. Although this feature may not be applicable to your needs, it does prove that µC/OS-II is a very robust RTOS.
µC/OS-II runs on a large number of processor architectures and ports. The vast number of ports should convince you that µC/OS-II is truly very portable and thus will most likely be ported to new processors as they become available.
µC/OS-II can be scaled to only contain the features you need for your application and thus provide a small footprint. Depending on the processor, on an ARM (Thumb mode) µC/OS-II can be reduced to as little as 6K bytes of code space and 500 bytes of data space (excluding stacks).
The execution time for most of the services provided by µC/OS-II is both constant and deterministic [2]. This means that the execution times do not depend on the number of tasks running in your application. µC/OS-II has been used in hundreds of products from companies all around the world are also using µC/OS-II in curriculum teaching the subject of real-time systems. This ensures that engineers in the workplace are trained and ready to use µC/OS-II in your products.
4.3. C/OS-II Feature
Portable
Most of C/OS-II is written in highly portable ANSI C, with target microprocessor specific code written in assembly language. Assembly language is kept to a minimum to take C/OS-II easy to port to other processors. Like Micro C/OS, Micro C/OS-II can be ported to a large number of microprocessors as long as the microprocessors provides a stack pointer and the CPU register can be pushed onto and popped from the stack. Also, the C compiler should provide either in-line assembly or language extension that allows you to enable and disable interrupt from C. C/OS-IIcan run on most 8-, 16-,32-, or even 64- bit microprocessors or microcontrollers and DSPs.
ROMable
C/OS-II was designed for embedded application. This means that if you have the proper tool chain (i.e. C compiler, assembler and linker/locater), you can embedded Micro C/OS-IIas part of a product.
Scalable
I designed C/OS-II so that you can use only the services you need in your application. This means that a product can use just a few C/OS-II services. While another product can have the full set of features. This allows you to reduce the amount of memory (both RAM and ROM) needed by C/OS-II on a per product basis. Scalability is accomplished with the use of conditional complication. Simply specify which features you need for your application or product.Preemptive
Micro C/OS-II is a fully preemptive real time kernel. This means that Micro C/OS-II always runs the highest priority task that is ready [1]. Most commercial kernel is preemptive, and C/OS-II is comparable in performance with many of them.
Multitasking
Micro C/OS-II can manage up to 64 tasks, however, the current version of the software reserve eight of these tasks for systems use. This leaves your application up to 56 tasks. Each task has a unique priority assigned to it, which mean that C/OS-II cannot do round robin. There are thus 64 priority levels.
Micro C/OS-II can manage up to 64 tasks, however, the current version of the software reserve eight of these tasks for systems use. This leaves your application up to 56 tasks. Each task has a unique priority assigned to it, which mean that C/OS-II cannot do round robin. There are thus 64 priority levels.
Deterministic
Execution time of all C/OS-II functions and services are deterministic. This means that you can always know how much time C/OS-II will take to execute a function or a service. Furthermore expect for one service, execution time all C/OS-II services do not depend on the number of tasks running application.
Robust and Reliable
Micro C/OS-II is based on C/OS, which has been used in hundreds of commercial application since 1992. C/OS-II uses the same core and most of the same functions as C/OS-II yet offer more features.
Micro C/OS-II is based on C/OS, which has been used in hundreds of commercial application since 1992. C/OS-II uses the same core and most of the same functions as C/OS-II yet offer more features.
4.4. MicroC/OS-II Concepts
Multitasking
Multitasking is the process of scheduling and switching the CPU between several tasks; a single CPU switches its attention between several sequential tasks. Multitasking is like foreground/background with multiple backgrounds [1]. Multitasking maximize the utilization of the CPU and also provides for modular construction of applications. One of the most important aspects of multitasking is that it allows the application programmer to manage complexity inherent in real-time application. Application programs are typically easier to design and maintain if multitasking is used.
Task
A task is a simple program that thinks it has the CPU all to itself. Each Task has
A task is a simple program that thinks it has the CPU all to itself. Each Task has
o Its own stack space
o A priority based on its importance
Task is assigned a unique priority .A task contains YOUR application code .A Real-Time application consists of several tasks executing concurrently. Task has its own set of CPU registers (backup in its stack) .Task is the basic unit for scheduling. Task status is stored in Task Control Block (TCB)
Task is assigned a unique priority .A task contains YOUR application code .A Real-Time application consists of several tasks executing concurrently. Task has its own set of CPU registers (backup in its stack) .Task is the basic unit for scheduling. Task status is stored in Task Control Block (TCB)
Task States
Each task typically is an infinite loop that can be in any one of five states: DORMANT, READY, RUNNING, and WAITING (for an event), and ISR (interrupted).
Each task typically is an infinite loop that can be in any one of five states: DORMANT, READY, RUNNING, and WAITING (for an event), and ISR (interrupted).
Dormant State
It is the state corresponds to a task that resides in memory but has not been made available to the multitasking kernel. Deleting task stored in dormant state.
It is the state corresponds to a task that resides in memory but has not been made available to the multitasking kernel. Deleting task stored in dormant state.
Ready State
A task is READY when it can execute but its priority is less than the currently running task. Simply say task is READY, but CPU is not available.
Running State
A task is RUNNING when it as control of the CPU. Simply we can say task under execution is called RUNNING state. 
Fig 4.1: Task States
Waiting State
A task is WAITING when it require the occurrence of an event (waiting for an I/O operation to complete , a shared resource to be available ,a timing pulse to occur, time to expire, etc….) .Here CPU is ready, but task is not ready.
ISR State:
A task is in the ISR state when an interrupt has occurred and the CPU is in the process of servicing the interrupt.
A task is in the ISR state when an interrupt has occurred and the CPU is in the process of servicing the interrupt.
Context Switch (or Task Switch)
When a multitasking kernel decides to run a different task, it simply saves the current task’s context (CPU register) in the current task’s context storage area-its stack [3]. Once this operation is performed, the new task’s context is restored from its storage area then resumes execution of the new task’s code. This process is called a context switch or task switch.
When a multitasking kernel decides to run a different task, it simply saves the current task’s context (CPU register) in the current task’s context storage area-its stack [3]. Once this operation is performed, the new task’s context is restored from its storage area then resumes execution of the new task’s code. This process is called a context switch or task switch.
Fig 4.2: Multitasking using a context switch
Context switching adds overhead to the application. The more registers a CPU has, the higher the overhead. The time required to perform a context switch is determined by how many register has to be saved and restored by the CPU. Performance of a real time kernel should not be judged by how many context switches the kernel is capable of doing per second.
Kernel
The kernel is the part of multitasking system responsible for the management of the tasks (i.e.., for managing the CPU’s time) and communication between tasks. The fundamental services provided by the kernel is context switching. The use real-time kernel generally simplifies the design of system by allowing the application to be divided into multiple tasks managed by the kernel. A kernel adds overheads to your system because it requires extra ROM (code space) and additional RAM for the kernel data structures. But most importantly, each task requires its own stack space, which has tendency to eat up your RAM quite quickly a kernel also consume CPU time (typically 2to 5 percent) [1].
Single-chip microcontrollers are generally not able to run a real-time kernel because they have very little RAM. A kernel allows you to make better use of your CPU by provided you with indispensible services a semaphore management, mailboxes, queue, time delay etc. once you design a system using a real-time kernel, you will not want to go back to the foreground/background system.
Single-chip microcontrollers are generally not able to run a real-time kernel because they have very little RAM. A kernel allows you to make better use of your CPU by provided you with indispensible services a semaphore management, mailboxes, queue, time delay etc. once you design a system using a real-time kernel, you will not want to go back to the foreground/background system.
Real-Time Kernel
Software that manages the time of a microprocessor or microcontroller. Ensures that the most important code runs first! Allows Multitasking: Do more than one thing at the same time. Application is broken down into multiple tasks (up to 63) each handling one aspect of your application. It’s like having multiple CPUs! Provides valuable services to your application: Time delays, Resource sharing, Inter task communication and synchronization
Software that manages the time of a microprocessor or microcontroller. Ensures that the most important code runs first! Allows Multitasking: Do more than one thing at the same time. Application is broken down into multiple tasks (up to 63) each handling one aspect of your application. It’s like having multiple CPUs! Provides valuable services to your application: Time delays, Resource sharing, Inter task communication and synchronization
Scheduler
Scheduler is the part of the kernel responsible for determining which task will run next [1]. Most real-time kernels are priority based. Each task is assigned a priority based on its importance. The priority of each task is application specific. Control is always given to the highest priority task ready to run.
Scheduler is the part of the kernel responsible for determining which task will run next [1]. Most real-time kernels are priority based. Each task is assigned a priority based on its importance. The priority of each task is application specific. Control is always given to the highest priority task ready to run.
Types of Kernel
There are two types of priority based kernels,
• Non-Preemptive Kernel
• Preemptive Kernel
Non-Preemptive Kernel
Non-preemptive kernels require that each task does something do explicitly give up control of the CPU [3]. 
Fig 4.3: Non-Preemptive Kernel
To maintain the illusion of concurrency; this process must be done frequently. Non-preemptive scheduling is also called cooperative multitasking; tasks cooperative with each other to share the CPU. Asynchronous events are still handled by the ISRs. An ISR can make a higher priority task ready to run, but the ISR always returns to the interrupted task. The new higher priority task will gain control of the CPU only when the current task gives up the CPU.
One of the advantages of a non-preemptive kernel is that interrupt latency is typically low. At the task level, non-preemptive kernel can also use non-reentrant function. Non –reentrant function can be used by each task without fear of corruption by another task. This is because each task a can run to complication before it relinquishes the CPU
Task-level response using a non-preemptive kernel can be much lower than with foreground/background system because task-level response is now given by the time of the longer task.
Require that each task does something to explicitly give up the control of the CPU [1]. Also called cooperative multitasking .ISR always returns to the interrupted task.
To maintain the illusion of concurrency; this process must be done frequently. Non-preemptive scheduling is also called cooperative multitasking; tasks cooperative with each other to share the CPU. Asynchronous events are still handled by the ISRs. An ISR can make a higher priority task ready to run, but the ISR always returns to the interrupted task. The new higher priority task will gain control of the CPU only when the current task gives up the CPU.
One of the advantages of a non-preemptive kernel is that interrupt latency is typically low. At the task level, non-preemptive kernel can also use non-reentrant function. Non –reentrant function can be used by each task without fear of corruption by another task. This is because each task a can run to complication before it relinquishes the CPU
Task-level response using a non-preemptive kernel can be much lower than with foreground/background system because task-level response is now given by the time of the longer task.
Require that each task does something to explicitly give up the control of the CPU [1]. Also called cooperative multitasking .ISR always returns to the interrupted task.
Preemptive Kernel
A preemptive kernel is used when system responsiveness is important. Because of this, MicroC/OS-II and most commercial real time kernel are preemptive. The highest priority task ready to run is always given control of the CPU [3]. When a task makes a higher priority task ready to run, the current tasks is preempted (suspended) and the higher priority task is immediately given control of the CPU. If an ISR makes a higher priority task ready, when the ISR complete the interrupted task is suspended and the new higher priority task is resumed.
A preemptive kernel is used when system responsiveness is important. Because of this, MicroC/OS-II and most commercial real time kernel are preemptive. The highest priority task ready to run is always given control of the CPU [3]. When a task makes a higher priority task ready to run, the current tasks is preempted (suspended) and the higher priority task is immediately given control of the CPU. If an ISR makes a higher priority task ready, when the ISR complete the interrupted task is suspended and the new higher priority task is resumed.
Fig 4.4: Preemptive Kernel
It is used when system responsiveness is important. High priority task ready to run is always given control of the CPU. Most real-time kernels are preemptive [1]. Application code using a preemptive kernel should not use non-reentrant functions or an appropriate mutual exclusion method should be applied to prevent data corruption. µC/OS-II is a Preemptive Kernel.
It is used when system responsiveness is important. High priority task ready to run is always given control of the CPU. Most real-time kernels are preemptive [1]. Application code using a preemptive kernel should not use non-reentrant functions or an appropriate mutual exclusion method should be applied to prevent data corruption. µC/OS-II is a Preemptive Kernel.
Starting mC/OS-II
Fig 4.5: Starting mC/OS-II 4.5. Initializing µC/OS-II
Program for Initializing 
4.6. Scheduling:(Delaying a Task)
Deciding whether there is a more important task to run. This occurs, when a task decides to wait for time to expire. When a task sends a message or a signal to another task [1]. When an ISR sends a message or a signal to a task. Occurs at the end of all nested ISRs.
The outcome is context switch if a more important task has been made ready-to-run or returns to the caller or the interrupted task.From the ready list a task is already running, and then the delay is given to a task. So that highest priority task able to run by the scheduling. Each task is assigned a unique priority level between 0 and OS_LOWEST_PRIO. From the ready list a task is already running, and then the delay is given to a task. So that highest priority task able to run by the scheduling. Each task is assigned a unique priority level between 0 and OS_LOWEST_PRIO.
Deciding whether there is a more important task to run. This occurs, when a task decides to wait for time to expire. When a task sends a message or a signal to another task [1]. When an ISR sends a message or a signal to a task. Occurs at the end of all nested ISRs.
The outcome is context switch if a more important task has been made ready-to-run or returns to the caller or the interrupted task.From the ready list a task is already running, and then the delay is given to a task. So that highest priority task able to run by the scheduling. Each task is assigned a unique priority level between 0 and OS_LOWEST_PRIO. From the ready list a task is already running, and then the delay is given to a task. So that highest priority task able to run by the scheduling. Each task is assigned a unique priority level between 0 and OS_LOWEST_PRIO.
Fig 4.6: The µC/OS-II Ready List I
Task priority OS_LOWEST_PRIO is always assigned to the idle task when Micro C/OS-II is initialized. Note that OS_MAX_TASKS and OS_LOWEST_PRIO are unrelated. Each task that is ready to run is placed in a ready list consisting of two variable, OSRdyGrp and OSRdyGrp[]. Task priorities are grouped (eight tasks per group) in OSRdyGrp. Each bit in OSRdyGrp indicates when a task in a group is ready to run. When the task is ready to run it also sets its corresponding bit in the ready table, OSRdyTbl[].
Here the scheduling is done by providing some delay and change the priority 1 to 0, and check for the next higher priority and that task will be move for running state[1] . Then the delayed task move to ready state. The next step will be task will move from old TCB to new TCB (task control block).
Task priority OS_LOWEST_PRIO is always assigned to the idle task when Micro C/OS-II is initialized. Note that OS_MAX_TASKS and OS_LOWEST_PRIO are unrelated. Each task that is ready to run is placed in a ready list consisting of two variable, OSRdyGrp and OSRdyGrp[]. Task priorities are grouped (eight tasks per group) in OSRdyGrp. Each bit in OSRdyGrp indicates when a task in a group is ready to run. When the task is ready to run it also sets its corresponding bit in the ready table, OSRdyTbl[].
Here the scheduling is done by providing some delay and change the priority 1 to 0, and check for the next higher priority and that task will be move for running state[1] . Then the delayed task move to ready state. The next step will be task will move from old TCB to new TCB (task control block).
Fig 4.7: The µC/OS-II Ready List II
C/OS-II always executes the highest priority task ready to run. The determination of which task has the highest priority, and thus which task will be next to run, is determined by the scheduler. 
Fig 4.8: The µC/OS-II Ready List III
Task level scheduling is performed by OSSched ().Task priority OS_LOWEST_PRIO is always assigned to the idle task when Micro C/OS-II is initialized. Note that OS_MAX_TASKS and OS_LOWEST_PRIO are unrelated. Each task that is ready to run is placed in a ready list consisting of two variable, OSRdyGrp and OSRdyGrp[]. Task priorities are grouped (eight tasks per group) in OSRdyGrp
Task level scheduling is performed by OSSched ().Task priority OS_LOWEST_PRIO is always assigned to the idle task when Micro C/OS-II is initialized. Note that OS_MAX_TASKS and OS_LOWEST_PRIO are unrelated. Each task that is ready to run is placed in a ready list consisting of two variable, OSRdyGrp and OSRdyGrp[]. Task priorities are grouped (eight tasks per group) in OSRdyGrp
Task Structure
• A task is an infinite loop
Void Task (void *p_arg)
{
Do something with ‘argument’ p_arg;
Task initialization;
For (;;) {
/* Processing (Your Code) */
Wait for event; /* Time to expire ... */
/* Signal from ISR ... */
/* Signal from task ... */
/* Processing (Your Code) */
}
}
4.8 Creating a Task with µC/OS-II
To makes it ready for multitasking. The kernel needs to have information about your task:Its starting address, its top-of-stack (TOS), its priority, Arguments passed to the task, other information about your task [1].
Extended Call
- You can also use OSTaskCreateExt() to create a task (preferable)
OSTaskCreateExt (void (*task) (void *parg),
Void *parg,
OS_STK *pstk,
INT8U prio,
INT16U id,
OS_STK *pbos,
INT32U stk_size,
Void *pext,
INT16U opt);
CHAPTER 5
HARDWARE IMPLEMENTATION
The hardware modules of the project are
· ARM
· Temperature sensor
· Graphical LCD
· Max-232
· Alarm
· LED
Block Diagram
Fig 5.1: Block diagram
5.1 Block Diagram Description
We have applied advanced real-time techniques software, that are intensively used in critical areas like space research and defense applications, to realize an industrial real time parameter Monitoring System. The heart of the system is a real-time kernel that uses preemptive scheduling to achieve multitasking on hardware platform. The Arm processor gets all relevant information from one source i.e. the remote terminal section. The temperature analysis data is plotted in convenient diagram in graphical LCD. The trend of all these parameters is available with a granularity of one minute.
In this project we are going to perform multitasking simultaneously. In Micro C/OS-II maximum number of task is 64, but here we going to perform up to 6 tasks the tasks like LED scrolling, alarm, temperatures sensor, graphical LCD, serial communication, relay are perform simultaneously.
Rtos for multitasking using arm controller is study paper, which can be adopted for various conditions, wherever the multi task operations are require with time constrain those are our project application area. For example missals launching, electronic engines, semaphore in ATM, nuclear plant, Robotics, boiler control in iron industries. In which we are take the temperature controlling operation in iron industry as our project
We have applied advanced real-time techniques software, that are intensively used in critical areas like space research and defense applications, to realize an industrial real time parameter Monitoring System. The heart of the system is a real-time kernel that uses preemptive scheduling to achieve multitasking on hardware platform. The Arm processor gets all relevant information from one source i.e. the remote terminal section. The temperature analysis data is plotted in convenient diagram in graphical LCD. The trend of all these parameters is available with a granularity of one minute.
In this project we are going to perform multitasking simultaneously. In Micro C/OS-II maximum number of task is 64, but here we going to perform up to 6 tasks the tasks like LED scrolling, alarm, temperatures sensor, graphical LCD, serial communication, relay are perform simultaneously.
Rtos for multitasking using arm controller is study paper, which can be adopted for various conditions, wherever the multi task operations are require with time constrain those are our project application area. For example missals launching, electronic engines, semaphore in ATM, nuclear plant, Robotics, boiler control in iron industries. In which we are take the temperature controlling operation in iron industry as our project
The following tasks are held by the controller while the operation:
Task-1:
Temperature sensor (i.e., ADC)
Task-2:
Graphical LCD (i.e., degree to graphical Fahrenheit)
How the multitasking achieved in our project
Task-3:
UART (i.e., digital data displaying)
Task-4:
LED toggle (ie.,8-bit data flow control)
Task-5:
Buzzer (i.e., alarm device)
5.2 Architecture of µC/OS-II
Board Support Package :( BSP)
In embedded systems, a board support package (BSP) is implementation specific support code for a given (device motherboard) board that conforms to a given operating system. It is commonly built with a boot loader that contains the minimal device support to load the operating system and device drivers for all the devices on the board [1].
Some suppliers also provide a root file system, a tool chain for making programs to run on the embedded system (which would be part of the architecture support package), and configurations for the devices (while running).
In embedded systems, a board support package (BSP) is implementation specific support code for a given (device motherboard) board that conforms to a given operating system. It is commonly built with a boot loader that contains the minimal device support to load the operating system and device drivers for all the devices on the board [1].
Some suppliers also provide a root file system, a tool chain for making programs to run on the embedded system (which would be part of the architecture support package), and configurations for the devices (while running).
Fig 5.3: Board Support Package
A board support package (BSP) is the common name for all board hardware-specific code. It typically consists of the following:
A board support package (BSP) is the common name for all board hardware-specific code. It typically consists of the following:
The boot loader
The OEM adaptation layer (OAL)
Board-specific device drivers
The BSP creation process involves the following tasks:
Developing a boot loader
Developing an OAL
Creating device drivers
Modifying run-time image configuration files
Chapter 6
HARDWARE SECTION
The hardware section divided into two units,
Ø Processing unit
Ø Monitoring uni
6.1. PROCESSING UNIT
6.1.1 ARM (ADVANCED RISC MACHINE)
A microcontroller is a computer-on-a-chip or a single-chip computer. The word ‘MICRO’ suggests that the device is small and the word ‘Controller’ suggests that the device can be used to control the objects, processors or events. Another term to describe a microcontroller is embedded controller [5]. This is because the microcontroller and its support circuits are often built into or embedded in the devices they control.
Microcontrollers are being widely used in most of the fields. Any device that measure, store, controls, calculates or display information is a candidate for putting a microcontroller inside. In desktop computer, you can find microcontroller inside keyboards, modems, printers and other peripherals. A microcontroller is similar to a microprocessor inside a personal computer. Both microprocessor and microcontroller contain a CPU.
Microcontrollers are being widely used in most of the fields. Any device that measure, store, controls, calculates or display information is a candidate for putting a microcontroller inside. In desktop computer, you can find microcontroller inside keyboards, modems, printers and other peripherals. A microcontroller is similar to a microprocessor inside a personal computer. Both microprocessor and microcontroller contain a CPU.
IMPLEMENTATION
The signals obtained from the sensors are amplified and are fed to the microcontroller [5]. The clock frequency of the microcontroller used here is 12MHZ.the microcontroller analyses these signals based on the software programs written in it. After analysis, the appropriate controlling action is taken by the microcontroller.
The signals obtained from the sensors are amplified and are fed to the microcontroller [5]. The clock frequency of the microcontroller used here is 12MHZ.the microcontroller analyses these signals based on the software programs written in it. After analysis, the appropriate controlling action is taken by the microcontroller.
INTRODUCTION OF ARM
Arm processors have merits of high performance low power consumption, low cost, etc. arm processors are the most widely used microprocessors amongst the 32 bit and 64 bit microprocessors.
At the time when ARM7 system architecture was just been accepted and applied, the embedded microprocessor market was overwhelmingly occupied by 8-bit and 16-bit microprocessors. However these microprocessors can’t meet the requirements of developing high-end applications such as mobile phones, modems, etc. These high-end products needed the 32-bit microprocessors processing power and higher programming code density then the 16-bit CISC processors [5]. In order to meet these requirements, a T variety of ARM architecture was developed. This T variety is called 16-bit Thumb instruction set. Thumb technology is one of the best characteristics of ARM technology. The 32-bit processors can be run with 16-bit Thumb instruction set. So, thumb is a bridge between the 16-bit older system and the 32-bit new system.
ARM architecture provided higher performance processor solution the users who were looking for higher performance processors. These features greatly increased the embedded development as well as ARM technology. The 16-bit microprocessors were not developed as people expected. The reason was complicated. Maybe one of the reasons was that the 32-bit ARM processors provided higher performance and lower price than the 16-bit processors and enabled the high-end embedded applications to jump to the new 32-bit generation [5].
The ARM is a 32-bit Reduced Instruction Set Computer (RISC) instruction set architecture (ISA) developed by ARM Limited. It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in terms of numbers produced. They were originally conceived as a processor for desktop personal computers by Acorn Computers, a market now dominated by the x 86 families by Intel and AMD. The relative simplicity of ARM processors made them suitable for low power applications. This has made them dominant in the mobile and embedded electronics market as relatively low cost and small microprocessors and micro-controllers.
ARM7TDMI is a core processor module embedded in many ARM 7 microprocessors including LPC2148. The ARM7TDMI core is a 32-bit embedded RISC processor. Its simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core [6].
Arm processors have merits of high performance low power consumption, low cost, etc. arm processors are the most widely used microprocessors amongst the 32 bit and 64 bit microprocessors.
At the time when ARM7 system architecture was just been accepted and applied, the embedded microprocessor market was overwhelmingly occupied by 8-bit and 16-bit microprocessors. However these microprocessors can’t meet the requirements of developing high-end applications such as mobile phones, modems, etc. These high-end products needed the 32-bit microprocessors processing power and higher programming code density then the 16-bit CISC processors [5]. In order to meet these requirements, a T variety of ARM architecture was developed. This T variety is called 16-bit Thumb instruction set. Thumb technology is one of the best characteristics of ARM technology. The 32-bit processors can be run with 16-bit Thumb instruction set. So, thumb is a bridge between the 16-bit older system and the 32-bit new system.
ARM architecture provided higher performance processor solution the users who were looking for higher performance processors. These features greatly increased the embedded development as well as ARM technology. The 16-bit microprocessors were not developed as people expected. The reason was complicated. Maybe one of the reasons was that the 32-bit ARM processors provided higher performance and lower price than the 16-bit processors and enabled the high-end embedded applications to jump to the new 32-bit generation [5].
The ARM is a 32-bit Reduced Instruction Set Computer (RISC) instruction set architecture (ISA) developed by ARM Limited. It was known as the Advanced RISC Machine, and before that as the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in terms of numbers produced. They were originally conceived as a processor for desktop personal computers by Acorn Computers, a market now dominated by the x 86 families by Intel and AMD. The relative simplicity of ARM processors made them suitable for low power applications. This has made them dominant in the mobile and embedded electronics market as relatively low cost and small microprocessors and micro-controllers.
ARM7TDMI is a core processor module embedded in many ARM 7 microprocessors including LPC2148. The ARM7TDMI core is a 32-bit embedded RISC processor. Its simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core [6].
ARM LPC2148 FEATURES
• 16/32-bit ARM7TDMI-S microcontroller in a tiny 64 package.
• 8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory [6].
• 128 bit wide interface/accelerator enables high speed 60 MHz operation.
• In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
• Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.
• Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip Real Monitor software and high speed tracing of instruction execution.
• USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
• In addition, the LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by DMA.
• One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14
• Analog inputs, with conversion times as low as 2.44 µs per channel.
• Single 10-bit D/A converter provide variable analog output.
• Two 32-bit timers/external event counters (with four capture and four compare (channels each), PWM unit (six outputs) and watchdog.
• Low power real-time clock with independent power and dedicated 32 kHz clock input [6].
• Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses
• (400 Kbit/s), SPI and SSP with buffering and variable data length capabilities.
• Vectored interrupt controller with configurable priorities and vector addresses.
• Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny 64 package.
• Up to nine edge or level sensitive external interrupt pins available.
• 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 µs.
• On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz and with an external oscillator up to 50 MHz.
• Power saving modes include idle and Power-down.
• Individual enable/disable of peripheral functions as well as peripheral clock scaling for Additional power optimization.
• Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out Detect (BOD) or Real-Time Clock (RTC).
Fig 6.1: ARM PIN DIAGRAM
• Single power supply chip with Power-On Reset (POR) and BOD circuits:
• –CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.
Description
This family introduces a new line of low voltage devices with the foremost traditional advantage of all ARMLPC2148 namely, high computational performance and a rich feature set at an extremely competitive price point. This feature makes the ARMLPC2148 family a logical choice for many high performance applications where cost is a primary consideration.
Pin Name | Pin Direction | Pin description |
X1 | Input | Crystal Oscillator Input - Input to the oscillator and internal clock generator circuits |
X2 | Output | Crystal Oscillator Output - Output from the oscillator amplifier |
EINT0 | Input | External Interrupt Input 0 - An active low/high level or falling/rising edge general purpose interrupt input. This pin may be Used to wake up the processor from Idle or Power-down modes. Pins P0.1 and P0.16 can be selected to perform EINT0 function. |
EINT1 | Input | External Interrupt Input 1 - See the EINT0 description above. Pins P0.3 and P0.14 can be selected to perform EINT1 function. |
EINT2 | Input | External Interrupt Input 2 - See the EINT0 description above. Pins P0.7 and P0.15 can be selected to perform EINT2 function. |
EINT3 | Input | External Interrupt Input 3 - See the EINT0 description above. Pins P0.9, P0.20 and P0.30 can be selected to perform EINT3 function. |
RESET | Input | External Reset input - A LOW on this pin resets the chip, causing I/O ports and peripherals to take on their default states, and the processor to begin execution at address 0x0000 0000 |
Table 6.1: Pin Description of ARM
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory [6].
The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website [5].
Fig 6.2: Block Diagram Of ARM Modes of Operation
ARM and Thumb are two different instruction sets supported by ARM cores with a “T” in their name. For instance, ARM7 TDMI supports Thumb mode. ARM instructions are 32 bits wide, and Thumb instructions are 16 wide. Thumb mode allows for code to be smaller, and can potentially be faster if the target has slow memory. Please consult documentation from your MCU vendor, or documentation from ARM, for additional information.
ARM Mode
The ARM 32-bit instruction set is the base 32-bit ISA used in the ARMv4T, ARMv5TEJ and ARMv6 architectures. In these architectures it is used in applications requiring high performance, or for handling hardware exceptions such as interrupts and processor start-up.
Condition Code | Meaning |
N | Negative condition code, set to 1 if result is negative |
Z | Zero condition code, set to 1 if the result of the instruction is 0 |
C | Carry condition code, set to 1 if the instruction results in a carry condition |
V | Overflow condition code, set to 1 if the instruction results in an overflow condition. |
Table 6.2: Condition codes
The ARM 32-bit ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex
The ARM 32-bit ISA is also supported in the Cortex™-A and Cortex-R profiles of the Cortex
architecture for performance critical applications, and for legacy code. Most of its functionality is subsumed into the Thumb-2 instruction set, which also benefits from improved code density.
ARM instructions are 32-bits wide, and are aligned on 4-byte boundaries. All ARM instructions can also be "conditionalised" to only execute when previous instructions have set a particular condition code.
This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction [5]. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect. This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.
This means that instructions only have their normal effect on the programmers’ model operation, memory and coprocessors if the N, Z, C and V flags in the Application Program Status Register satisfy a condition specified in the instruction [5]. If the flags do not satisfy this condition, the instruction acts as a NOP, that is, execution advances to the next instruction as normal, including any relevant checks for exceptions being taken, but has no other effect. This conditionalisation of instructions allows small sections of if- and while-statements to be encoded without the use of branch instructions.
THUMB Mode
Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM, instruction set and a 16-bit THUMB instruction set. The THUMB set’s 16-bit instruction length means that a program will occupy lesser memory compared to 32-bit instruction set. It allows more code to occupy lesser memory. Most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
Essentially, the ARM7TDMI-S processor has two instruction sets: The standard 32-bit ARM, instruction set and a 16-bit THUMB instruction set. The THUMB set’s 16-bit instruction length means that a program will occupy lesser memory compared to 32-bit instruction set. It allows more code to occupy lesser memory. Most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
TDMI refers to the following:
T: capable of executing the Thumb instruction Set
D: JTAG based on-chip debugging
M: Multiplier-And-Accumulate (MAC) unit required for DSP applications
I: Icebreakers debug module supporting hardware breakpoints and watch points, stalling the system for debugging
The ARMTDMI-S processor employs a unique architectural strategy knows as THUMB, Which makes it ideally suited to high-volume applications with memory restrictions or applications where code density is an issue.
The ARMTDMI-S processor employs a unique architectural strategy knows as THUMB, Which makes it ideally suited to high-volume applications with memory restrictions or applications where code density is an issue.
Thumb’s Advantages
The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently.
When processing 32-bit data, a 16-bit architecture will take at least two instructions to perform the same task as a single ARM instruction. However, not all the code in a program will process 32-bit data and some instructions, like Branches, do not process any data at all.
THUMB also has a major advantage over other 32-bit architectures with 16-bit instructions. This is the ability to switch back to full ARM code and execute at full speed.
The major advantage of a 32-bit (ARM) architecture over a 16-bit architecture is its ability to manipulate 32-bit integers with single instructions, and to address a large address space efficiently.
When processing 32-bit data, a 16-bit architecture will take at least two instructions to perform the same task as a single ARM instruction. However, not all the code in a program will process 32-bit data and some instructions, like Branches, do not process any data at all.
THUMB also has a major advantage over other 32-bit architectures with 16-bit instructions. This is the ability to switch back to full ARM code and execute at full speed.
6.3. Monitoring Section
6.3.1. Temperature Sensor The LM35 does not require any external calibration or trimming to provide typical accuracies of at room temperature and °C over a full -55 to +150°C temperature range. Low cost is assured by trimming and calibration at the wafer level [6]. The LM35’s low output impedance, linear output, and precise inherent calibration make interfacing to readout or control circuitry especially easy. It can be used with single power supplies, or with plus and minus supplies.
Features
Calibrated directly in ° Celsius (Centigrade)
Linear + 10.0 mV/°C scale factor
Fig 6.3: Temperature Sensor
0.5°C accuracy guarantee able (at +25°C)
Rated for full -55° to +150°C range
Suitable for remote applications
Low cost due to wafer-level trimming
Operates from 4 to 30 volts
Less than 60 µA current drain
Low self-heating, 0.08°C in still air
Nonlinearity only ±¼°C typical
Low impedance output, 0.1 Ohm for 1 mA load
Fig 6.4: Basic Centigrade Temperature Sensor
As it draws only 60 µA from its supply, it has very low self-heating, less than 0.1°C in still air [6]. The LM35 is rated to operate over a -55° to +150°C temperature range, while the LM35C is rated for a -40° to +110°C range (-10° with improved accuracy).
As it draws only 60 µA from its supply, it has very low self-heating, less than 0.1°C in still air [6]. The LM35 is rated to operate over a -55° to +150°C temperature range, while the LM35C is rated for a -40° to +110°C range (-10° with improved accuracy).
The LM35 series is available pack. Aged in hermetic TO-46 transistor packages, while the LM35C, LM35CA, and LM35D are also available in the LM35 series are precision integrated-circuit temperature plastic TO-92 transistor package. The LM35D is also avail- sensors, whose output voltage is linearly proportional to the table in an 8-lead surface mount small outline package and a Celsius (Centigrade) temperature. The LM35 thus has a plastic TO-220 package.
6.3.2. GLCD
This paper and project outline the design of a graphical LCD driver for the Crystalfontz CFAG12864B series (128 x 64 pixel) graphical display which can be easily modified to drive any Samsung KS0108 based graphical LCD.
Design and Implementation
The CFAG12864B
The CFAG12864B is a 128 x 64 pixel graphical LCD with backlight. It is driven by 2 64 x 64 pixel Samsung KS0108 drivers. Figure 1 shows an image of what the LCD looks like with a sample output of a tractor. The actual view area of the LCD is 60 mm x 32.6 mm [6].
Fig 6.6: the CFAG12864B graphical Liquid Crystal Display
Pin Assignments
Setting up the LCD and turning it on
The Appendix contains a detail pin-out of the LCD but the important pins for this section are as follows:
Table 6.3: GLCD Pin Assignments
In order for the LCD to power up, Pin 1 must be connected to + 5V, Pin 2 must be connected to GND and Pin 3 & Pin 18 must be connected as illustrated in Fig. 2. Adjusting this value adjusts the contrast but the Pins must be connected in this way in order for the image to be seen on the screen (if it isn’t there is essentially no contrast and nothing will be displayed [6].
Fig 6.7: LCD pins connection
6.2.3 LED: (light emitting diode)
When a light-emitting diode is forward biased (switched on), electrons are able to recombine with electron holes within the device, releasing energy in the form of photons. This effect is called electroluminescence and the color of the light (corresponding to the energy of the photon) is determined by the energy gap of the semiconductor. An LED is often small in area (less than 1 mm2), and integrated optical components may be used to shape its radiation pattern.
LEDs present many advantages over incandescent light sources including lower energy consumption, longer lifetime, improved robustness, smaller size, faster switching, and greater durability and reliability. LEDs powerful enough for room lighting are relatively expensive and require more precise current and heat management than compact fluorescent lamp sources of comparable output. Light-emitting diodes are used in applications as diverse as replacements for aviation lighting, automotive lighting (particularly brake lamps, turn signals and indicators) as well as in traffic signals[6].
Fig 6.8: Structure of LED
6.2.4. MAX 232
Introduction:
MAX-232 is primary used for people building electronics with an RS-232 interface [6]. Serial RS-232 communication works with voltages (-15V ... -3V for high) and +3V ... +15V for low) which are not compatible with normal computer logic voltages. To receive serial data from an RS-232 interface the voltage has to be reduced, and the low and high voltage level inverted. In the other direction (sending data from some logic over RS-232) the low logic voltage has to be "bumped up", and a negative voltage has to be generated, too. In telecommunications, RS-232 is a standard for serial binary data interconnection between a DTE (Data terminal equipment) and a DCE (Data Circuit-terminating Equipment).
Fig 6.9: Pin Diagram of Max 232
RS232
Fig 6.10: RS232 DB 9 Male Pin Out
Devices which use serial cables for their communication are split into two categories. These are DCE (Data Communications Equipment) and DTE (Data Terminal Equipment.) Data Communications Equipment is devices such as your modem, TA adapter, plotter etc while Data Terminal Equipment is your Computer or Terminal.
CHAPTER 7
SOFTWARE SECTION
7.1. Keil IDE Software Keil IDE is a windows operating system (os) software program that runs on a PC to develop applications for ARM microcontroller and digital signal controller [7]. It is also called Integrated Development Environment or IDE because it provides a single integrated “environment” to develop code for embedded microcontroller. The rest of this briefly explains embedded system development and how Keil IDE is used.
An embedded system is typically a design making use of the power of a small microcontroller, like a Phillips ARM. These microcontrollers combine a microprocessor unit(like the CPU in a desktop PC) with some additional circuits called “peripherals”, plus some additional circuits on the same chip to make a small control module requiring few other external devices. This single device can then be embedded into other electronic and mechanical device for low-cost digital control [7].
Keil software is the leading vendor for 8/16-bit development tools (ranked at first position in the 2004 embedded market study of the embedded system and EE times magazine).Keil software is represented worldwide in more than 40 countries, since the market introduction in 1988; the Keil C51 compiler is the de facto industry standard and supports more than 500 current 8051 device variants [7]. Now, Keil software offers development tools for ARM.
Keil software makes C compilers, macro assemblers, real-time kernels, debuggers, simulators, integrated environments, and evaluation boards for 8051, 251, ARM and XC16x/C16x/ST10 microcontroller families.
An Example of using Keil uVision3 for creating Keil ARM’s Project:
1. Open Keil uVision Program which is Text Editor of Keil-ARM uses for writing C Language Source Code Program as inthe picture.
2. Set default value to translate uVision3 Code to use withKeil uVision3 Program and Keil ARM.
There are 3 default values of them –Use Keil ARM Tools, UseGNU Tools, andUse ARM Tools- in this case, select “Use Keil ARM Tools” then assign position of folder to savedefault value of Keil ARM Program. Generally, it is“C:\Keil\ARM\”, but if you install Keil in other position,you need to change correctly as in the picture.
3. Create new Project File. Click Project New Project then set the position of folder that you want to save with its title. For example, if you want to create Project File named LED_BLINK and save in folder named LED, you can set them by yourself [7]. After you fill its name in File name blank, click save project File as in the picture.
Program proceeding waits for users to set No. of MCU after you saved Project File. No.of Philips’MCU in ET-ARM STAMP LPC2119 Board is LPC2119 then click OK as in the picture Next, users need to confirm to copy File Startup of Keil to use with Philips’MCU or not because Startup File is the beginning value of MCU such as Stack values and default value to use with Phase-Lock-Loop. You should set values of them before starting to run your written program; otherwise MCU is added orders to run by the written program. Startup File of Keil-ARM is Assembly Language and is set to work with Keil Development. So, there are some different specifications to use. You can’t use Startup File with ET-ARM STAMP LPC2119 Board immediately; you need to change some default value. Using Keil ARM Program to translate orders, users need to correct Startup File to set value as well as ET-ARM STAMP LPC2119 Board form. In this case, select “No” to protect Keil uVision3 copy Startup File of Keil-ARM to use in this Project.
4. Copy File named ”Startup.s” that is in ETT’s CD-ROM in folder named “SOURCE_KEIL” into the same position of New Project File File named “Startup.S” which is contained orders of ARM7 in Assembly Language uses to set the necessary default value of MCU such as setting Stack value, Initial Phase-Lock-Loop, MAM Function, and MCU”s Vector. If you add “Startup.s File” from Keil or copy file from other source to use with “ET-ARM STAMP LPC2119 Board”, its program in Startup is different, and it will effect on written program [7]. 
5. Select Option of Project File. Click Project Option for target ‘target 1’ then select Tab of Target for setting MCU Target value. The proceeding is; X-TAL is 19.6608 MHz and set the MCU Memory is condition to translate Keil ARM Program as in the picture. 
6. Start to write Source Code with C Language by click File New… The Text File is displayed. In the first time, you should set its name as “Text1” as in the picture.
After finished to write program in C Language, you click save this file with its surname as”.C”. For example, File Save As… and then set its file name as “.main.c” as in the picture.
After saved file, colour of letters in this program is changed with its function such as Comment, Variable, and Order. It is the good point of Keil uVision3 program and users use it easily as in the picture.
7. Add File with Project File by click Project Components, Environment, Books[7]… then select Tab Project Components and then select Add File In the first time, you should select Files of type as “C Source files(*.c) because it shows other files name in Source Code. Click icon file named “main.c” then select Add file named “Startup.s” to Project File Set new File of type as “ASM Source files (*.s*;*.src;*.a*)”. Its file named Startup.s is shown in file name blank, click icon file “Startup.s”, and then select Add.
Fig 7.1: Output Screenshot of KEIL
8. Translate program by click Projects Rebuild all target files. Keil uVision3 Program can order Keil ARM Program to translate program immediately After translated program correctly without any mistake (0 Error and 0 Warning), you will get the HEX File name as same as the Project File name. Users can download HEX File to MCU immediately [7].
Flash magic can control the entry into ISP mode of some microcontroller devices by using the COM port handshaking signals to control the device. Typically the handshaking signals are used to control such pins as Reset, PSEN and VCC. The exact pins used depend on the specific device. When this feature is supported, Flash Magic will automatically place the device into ISP mode at the beginning of an ISP operation.
Fig 7.2: Screenshot of Flash Magic
Flash Magic will then automatically cause the device to execute code at the end of the ISP operation.
CHAPTER-8 CONCLUSION AND FEATURE WORKS
8.1 ConclusionThe system is thus designed and tested and found, thus the system is working properly. Proper set of instruction suitable for a specific application always lead to a better system
The science is a vast field and invention of new system is a part of it so still better systems. Can be invented and implemented with a bit of intelligence
8.2 Feature Works
The most of the current kernels (RTOS) are successfully used in today’s real-time embedded systems, but they increase the cost and reduce flexibility.
Next generation real-time operating systems would demand new operating systems and task designs to support predictability, and high degree of adaptability. So our project can be further improve vise by utilization of upcoming new RTOS according to your application.
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